Logic Equivalence Checking (LEC), Static Timing Analysis (STA), Python, Tcl, RTL Synthesis, Low Power UPF IEEE 1801, primetime, Fishtail

Formal verification (LEC), Static Timing Analysis (STA), Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management

Nosql, Databases, Docker, OLAP, Distributed Systems, Rest Apis, Python, Kubernetes, AWS, Oltp, AI-native development

Unix, Shell, Linux, Verilog, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, LINT, Low Power

Java, Distributed Systems, C++, Kafka, Microservice Architecture, Spark Streaming, metrics, Python, Logging, Go, Flink, Beam, Samza, tracing, Pub-Sub Systems

Perl, Python, Tcl, LINT, Synthesis, cdc, SoC integration, ASIC SOC design, systemverilog, Dft, RTL Verilog, Bluetooth SoCs, Timing Analysis, UPF power domains

Perl, Python, Tcl, FineSim, Matlab Simulink, Cadence Xcelium, CustomSim, mixed-signal verification, Uvm, systemverilog, Spectre, Synopsys VCS, AMS Designer, Cadence Virtuoso, Verilog-A

Numpy, Git, Pytorch, Pandas, Python, OpenAI’s GPT models, Hugging Face, prompt engineering