Formal verification (LEC), Static Timing Analysis (STA), Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management

Perl, Python, Tcl, FineSim, Matlab Simulink, Cadence Xcelium, CustomSim, mixed-signal verification, Uvm, systemverilog, Spectre, Synopsys VCS, AMS Designer, Cadence Virtuoso, Verilog-A

Logic Equivalence Checking (LEC), Static Timing Analysis (STA), Python, Tcl, RTL Synthesis, Low Power UPF IEEE 1801, primetime, Fishtail

Nosql, Databases, Docker, OLAP, Distributed Systems, Rest Apis, Python, Kubernetes, AWS, Oltp, AI-native development

Java, Cassandra, Spring Boot, Kafka, J2EE, Spring Cloud, Google Cloud, Spring, Microservices, Jms, Docker, MySQL, Openshift, MongoDB, Oracle, Azure, Kubernetes, AWS, CI/CD

Unix, Shell, Linux, Verilog, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, LINT, Low Power

Perl, Python, Tcl, primetime, RTL-to-GDS recipes, Physical Design, Fusion Compiler, Synopsys Fusion Design Platform, IC Compiler II, AI ML optimization tools, Synopsys DSO.ai

Java, Distributed Systems, C++, Kafka, Microservice Architecture, Spark Streaming, metrics, Python, Logging, Go, Flink, Beam, Samza, tracing, Pub-Sub Systems

Perl, Python, Tcl, LINT, Synthesis, cdc, SoC integration, ASIC SOC design, systemverilog, Dft, RTL Verilog, Bluetooth SoCs, Timing Analysis, UPF power domains