C, Numpy, Ethernet, Matlab, Mentor Veloce, LPDDR, high-speed Serdes, Cadence Palladium, FPGA designs, Synopsys Zebu, FPGAs, DSP designs, MIPI, post-silicon bring-up, signal processing functionality, pre-silicon validation, System Verilog RTL Code, ASICs, AMBA protocols, Diagnostics Firmware development

C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog, SVA

C, Verilog, Verdi, Xcellium, JasperGold, Uvm, systemverilog

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

Timing Closure, Synthesis, primetime, Physical design implementation, floorplanning, Synopsys Fusion Compiler, Cadence Innovus, Tempus

regulators , temperature sensors , Dll, Reference Circuits, PMU circuits, RC Oscillators, Validation, Mixed-Signal Design, Crystal Oscillators, Analog design and simulation tools, Switching Regulators, Pll, Signal Chains, Oscillator, Precision Comparators, Analog IC Design, characterization, Debug, Silicon bring-up