C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog, SVA

Sqlalchemy, Grafana, React, Typescript, Terraform, Postgres, Python, Sentry, Redis, FastAPI, Kubernetes, GitOps, PostHog, Tailwind, TurboPuffer, GitHub Actions, Temporal, Next.js, OpenTelemetry, Pydantic, GKE, LLMs, Anthropic, AKS, Expo, Argo CD, OpenAI, Gemini

C, Verilog, Verdi, Xcellium, JasperGold, Uvm, systemverilog

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

Numpy, Git, Pytorch, Pandas, Python, OpenAI’s GPT models, Hugging Face, prompt engineering

Engineering Data Management (EDM) workflows, altium , Jira, Git, Release management, Engineering data management, Cadence, Siemens Xpedition, Windchill, Altium 365 Workspace, Configuration control, Teamcenter, Digital engineering practices, Workflow automation, Tool integrations, Library governance, Lifecycle governance

Bluetooth, Zephyr, Spi, MATLAB, Jtag, Freertos, I2c, Uart, Gpio, C Programming, Ble, Timers, Embedded Software Firmware Development, Low-level device drivers, Threadx, Clock management, LoRa, DMA, Low-power embedded design, Sleep wake mechanisms, SWD, Protocol analyzers, Object-oriented concepts, Wi-Fi, UWB MAC, Embedded debugging tools, RTOS environments, Logic analyzers, ARM Cortex-M, Power sequencing, UCI

nand flash , automation, Debugging, Log Analysis, C Programming, Garbage Collection, test generation, SSD Storage Firmware Development, SLC MLC QLC concepts, SSD flash translation layer, AI-assisted engineering tools for firmware development, Wear leveling, digital hardware design, Firmware design and debug