Fpga, Vcs, Perl, Verilog, Python, ASIC design flow, LINT, Verdi, Design Compiler, cdc, RDC tools, RTL, Conformal, Unix/Linux computing environment, systemverilog, SoC architectures, primetime, spyglass, Timing constraints for synthesis and STA

Solidworks, CAD Creo, Optomechanical assemblies, Vibration stiffness, Pneumatics, gd&t, Troubleshooting, Mechanical Drawings, Analytical Skills, Thermal effects, Alignment processes, Tolerance control, Tolerance stack up analysis, Sensors, Electro Mechanical stage, Precision testing and measuring instruments, Root Cause Analysis, Data Analysis, Error budgeting