Device Testing, high voltage device development, process integration technology development, Failure Analysis, high voltage test structure layout, Reliability Testing, device optimization, CMOS HV process schemes, design of experiment for process development, device physics

Punch List, Procedure Qualification Test, Quality Plan, Quality Manual, Material Receiving Inspection, Post-Test Checklist, Weld Joint Preparation, Pre-Test Checklist, Method Statement

MDSAP, Iso 13485, Iso 9001, Validation, Continuous Improvement, Product Quality Engineering, FDA 21 CFR Part 820, Risk Management, IQ OQ PQ, Data-driven Analysis, Process Validation, Control Plans, Regulatory Compliance, Pfmea

iso standards, SAP systems, Dfmea, Lean Continuous Improvement methodologies, Pfmea, Tooling Design, Statistical tools for process capability analysis, Process troubleshooting, ANOVA testing

Electrical Engineering (including power engineerin, Configuration Management, Risk Identification, Leading Organizational Change, Programme and Project Management, Enterprise Resource Planning, build process, Risk Mitigation, packaging engineering, Cost Evaluation, Process Ownership, Buying Strategy, Work Preparation, customer qualification, Project Lifecycle Management, Qualification Process

Iso 13485, Engineering Drawings, Spc, IATF 16949, Control Plan, Plastic Injection Molding, Cp, FAI, Iso 9001, Ppap, CMM Vision Measurement Systems, Pfmea, Msa, Cpk

process qualification , semiconductor packaging , test procedures , process development, advanced packaging technologies, panel-level bonding, machine setup, application recipes, Flip-Chip, motion control systems, PoP, Failure Analysis, Troubleshooting, semiconductor equipment integration, Alignment, die bonding equipment, Calibration