C, C++, Bash, Perl, Verilog, Python, Tcl, IP architecture, Debug, stimulus development, verification planning, Digital Design, Uvm, systemverilog, scoreboards, assertions, functional coverage

Verilog, C, Python, Perl, Gdb, Indago, SOC design, Cadence

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP

Ovm, Verilog, System Verilog, C, Systemc, PERL, Shell script, Assembly Language, dpi, SoC Verification, Uvm, Emulation

code coverage , MATLAB, Functional Coverage, large-scale regression debugging, System Verilog UVM, directed testing, constrained-random verification, Fixed-Point Designer, C reference models, DSP and arithmetic data paths, model-based verification, RAL

Verilog, formal verification, VHDL, Chisel, JasperGold, VC Formal, Object-oriented Programming, Formal Abstraction Techniques, systemverilog

Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

C, C++, Ci, Git, Python, protocol analyzers, error injection, Emulation, fault modeling, agile development practices, UCIe, Axi, Keysight, Teledyne LeCroy, DMA, silicon debug tools, ASIC front-end architecture