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Showing 2 jobs
Skills:
rtl verification , Verilog, systemverilog, FSM design, Rtl Design, Axi, reset strategy, debugging methodologies, APB, BUS Protocols, SoC design flow, Simulation, timing considerations, AHB, datapath design, clock-domain handling
Skills:
rtl verification , Verilog, reset strategy, Simulation, timing considerations, datapath design, FSM design, Rtl Design, clock-domain handling, systemverilog, Axi, debugging methodologies, APB, BUS Protocols, AHB, SoC design flow
