Automation Frameworks, Perl, Verilog, Data Analytics, Pattern Recognition, Python, anomaly detection, Synopsys VCS, NAND Validation, Electrical Failure Analysis, AI ML Techniques

Perl, Verilog, Python, Tcl, Synthesis, VHDL, Place Route, Timing Closure, Timing Analysis, RTL-to-GDS implementation, timing and logic ECOs

Perl, Linux Shell Scripting, Python, Tcl, DFT instruments, EDA Tools, make, ASIC development

synopsys primetime , Ecos, routing, Perl, Python, Tcl, Sta, Fusion Compiler, ICC2, LEC, Physical Design, Cadence Genus, noise analysis, Cadence Tempus, Logic Synthesis, cell sizing, timing convergence, Innovus, Timing Constraints, Synopsys Design Compiler, Timing Closure, Placement

containerization , python, Technical Documentation, Asynchronous programming, Nosql, Streaming, context engineering, a/b testing, ragas, chatbot development, Content Moderation, retrieval-augmented generation, vector search, red-teaming, policy enforcement, ci/cd, g-eval, Caching, cost/latency budgeting, hybrid search, batching, Mentoring, llm development, prompt engineering

Promotion of Innovation, Data Analysis, Reliability Test Flow Development, Cross-Functional Collaboration, DRAM architecture, scripting tools such as Python or JMP, DPM reduction, Risk Management, Reliability Test Plan and Execution, Project Management, Root Cause and Resolution of Qual and RMA Device Issues, CMOS technology, Statistics, Process Conversions and HVM, basic device physics, Technical Decision Making