Test Automation, Python Scripting, Verification Tools, Digital Design, FPGA Development, Debugging Skills, ModelSim Expertise, Verification Planning, SystemVerilog Knowledge, UVM Methodology

C, C++, Shell, Perl, Verilog, Debugging, System Verilog, Python, Tcl, UVM methodology, Metric Driven Verification, directed and constrained random methodologies, formal verification methodologies, assertions, functional and code coverage

bandwidth management , Machine Learning, Artificial Intelligence, SystemVerilog Assertions, Specman E, Debug, formal tools, IP subsystem SoCs, congestion control, AI ML accelerators, systemverilog, memory system architecture, vector processing units, ASIC standard interfaces, packet processing, Verification, Universal Verification Methodology

Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Perl, Verilog, Ovm, Scripting Languages, System Verilog, Python, Rtl Design, Verdi, simulation debug tools, make, Uvm

code coverage , System Verilog, IC verification tools, Cover groups, DIMM, DDR5, Uvm, DDR4, Functional coverage, Assertions, LPDDR5

C, C++, Bash, Perl, Verilog, Python, Tcl, IP architecture, Debug, stimulus development, verification planning, Digital Design, Uvm, systemverilog, scoreboards, assertions, functional coverage

Modeling, automation techniques, reusable intellectual property, circuit design verification, silicon correlation, analog and mixed-signal IC design, semiconductor device physics, CMOS technologies, AI-driven engineering tools, product qualification, DRAM, advanced process nodes