Process technologies, Analog IC design, Simulation Tools, Reliability issues, Test modes, Drivers, POR, High voltage high power operation, POL ICs, LDO, Oscillators, DC-DC converter power stages, Bandgap, Current sensing

clocking , Ovm, Python, System Verilog, Perl, LINT, interconnect, cdc, Reset, Verilog Hdl, Uvm, UPF, CLP flows, Micro-architecture specifications, Synthesis, Dft, RDC, SoC Infrastructure, Debug, Power optimization methodologies, Interrupts, digital hardware design, power management, Physical implementation, Constraint development, Timing Analysis

static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols

synchronicity , Unix, Perforce, Python, Shell Scripting, Git, Perl, Tcl, substrate noise analysis, Skill, Cadence custom IC Virtuoso platform, Cadence SKILL, starRC, Layout Automation, Calibre Physical Verification, ICV LVS, Analog Design environment, EMIR drop, agentic AI flows, finesim, Parasitic Extraction, PrimeSim, Virtuoso suite, SVRF

Integration, Programming Languages, design verification methods, scripting tools, RTL to GDS Flow, Validation, architecture and design tools, Verification, ASIC Design, virtuoso

layout interaction, silicon bring-up, design sign-off, behavioral modeling, Analog Circuit Design, mixed-signal IC design, post-layout verification, high-speed oscilloscopes, Synopsys Custom Compiler, Spectre, high-speed interfaces, BERTs, Compliance Testing, Parasitic Extraction, Cadence Virtuoso, Hspice

C, Numpy, Ethernet, Matlab, Mentor Veloce, LPDDR, high-speed Serdes, Cadence Palladium, FPGA designs, Synopsys Zebu, FPGAs, DSP designs, MIPI, post-silicon bring-up, signal processing functionality, pre-silicon validation, System Verilog RTL Code, ASICs, AMBA protocols, Diagnostics Firmware development