Formal Property Verification (FPV), Perl, System Verilog, Python, ASIC SoC Design Verification, Uvm

arm architecture , C, C++, ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, pre-silicon SoC verification, performance verification, PCIe CXL Controller PHY IPs and protocols, DDR protocols, Memory Controller PHY IPs

FineSim, Synopsys VCS, SerDes verification, analog mixed signal verification, Xcelium, Verilog-AMS, high-speed design, SystemVerilog-RNM, Cadence Virtuoso, Uvm, Spectre

Feature Validation Test (FVT), Garbage Collection, Nvme, Test Strategies, Debugging, Pcie, Automation Frameworks, Python, Automated reporting systems, Wear levelling, Qualification methodologies, CI/CD-integrated validation solutions, Firmware verification methodologies, AI-centric storage workloads, Bad block management, Validation plans, Error injections

LabVIEW, C, Python, SoC System-on-Chip, voltage regulators, precision measurement techniques, bench characterization of Analog Digital and Mixed-Signal IPs, Microcontrollers, reference circuits

Pcie, Verification IPs, assertions, CXL, Uvm, system-level verification, test sequences, COSMOS software suite