Tuning, Os Internals, C, Device Drivers, C++, virtualization, Memory Management, Jtag, Scripting Languages, secure boot flows, CPU architecture, multi-core systems, performance profiling, Kernel Development, RISC-V, ARM architectures, interrupt handling, debug tools, power management integration, silicon bring-up, assembly

Gcp, Shell scripting, C Programming, Azure, AWS, Git, Automation Frameworks, AI/ML technologies, Multi-cloud infrastructure, Performance profiling, Database internals tuning and optimization, Jenkins pipelines, Linux FreeBSD-based systems, Networking concepts and protocols

static timing analysis, RISC CPU IP, CPU microarchitecture, IP integration, Floor Planning, silicon bring-up, Timing Analysis, Emulation, Physical Design, chip validation, Rtl Design, CDC analysis, ARM CPUs, SoC design methodology, characterisation, Synthesis, linting, Timing Closure, Verification, equivalence checking, BUS Protocols

Tcl, Python, Perl, Innovus, Physical Formal Verification, Cross-Functional Collaboration, LEC, primetime, EDA Tools, Fusion Compiler, Calibre, Red Hawk, Tempus, Timing Closure STA, RTL-to-GDSII Execution, Programming Scripting, VCLP, PPA Optimization

bist , Verilog, C, Vcs, Python, AHB, microcontroller platforms, Timing Analysis, systemverilog, digital timing constraints, DFT methodologies, Cadence Virtuoso, APB, Axi, ASIC tool flows, Questa, Timing Constraints, high-speed SerDes, ATPG, FPGAs, AMBA, XCelium, SOC interconnect fabrics, Genus Design Compiler, Asic verification, Scan Insertion, ASIC synthesis

Software Design, Sql, Web Services, Ruby, C, Distributed Systems, Java, Database Design, Python, Objective-c

Tcl, Verilog, Python, Perl, MBIST, Siemens Mentor Tessent, systemverilog, ATPG, Pre-Silicon test planning, DFT methodologies, DFT Compiler, low power concepts, RTL design for DFT, Scan, IJTAG, Synopsys TetraMAX, DFT Integration Verification, Memory Repair