Senior / Staff Physical Verification Engineer

About the Role

Our client is a globally operating technology company specialising in high-performance computing infrastructure and AI cloud services, with a diversified energy portfolio spanning multiple continents and a strong focus on next-generation chip design. They are headquartered in Singapore and are at the forefront of developing industry-grade ASIC solutions on leading-edge process nodes. This role offers a unique opportunity to take full ownership of physical verification signoff at both block and full-chip levels, working at the intersection of circuit design and backend implementation in a fast-paced, high-impact environment.

Key Responsibilities

Execute comprehensive Physical Verification (PV) signoff for advanced-node ASIC/SoC designs, covering DRC, LVS, ERC, ANT, ESD, PERC/Reliability, density/fill, and all foundry-mandated tape-out checks

Monitor and manage PV runs end-to-end, including hierarchical and flat execution modes, runtime and resource optimisation, result tracking, issue prioritisation, and milestone-driven closure toward tape-out

Collaborate closely with Place & Route engineers to identify and resolve full-chip layout integration issues

Support the complete physical design flow from netlist through to GDSII delivery, ensuring design quality and process compliance at every stage

Develop and implement automation solutions to streamline tape-out workflows and improve team efficiency

Contribute to internal physical design methodology, scripting libraries, and flow automation using Perl and Tcl

Partner with circuit design and backend teams to align on signoff criteria and drive timely tape-out execution

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related discipline

Minimum 5 years of hands-on physical verification experience on advanced process nodes, with experience at N4 or below strongly preferred (experience specifically on TSMC nodes is a bonus)

Demonstrated proficiency with Calibre or equivalent industry-standard physical verification tools

Solid understanding of the end-to-end IC design flow, from front-end design through backend implementation and full signoff

Prior tape-out experience is required familiarity with Python, Perl, Tcl, or Make scripting for flow automation (is a bonus)

If you are passionate about technology and meet the above requirements, please don't hesitate to apply. Please note that only shortlisted candidates will be contacted. Appreciate your understanding. Data provided is for recruitment purposes only.

Dada Consultants Pte Ltd

Website: www.dadaconsultants.com

EA License No.: 18S9037

Business Registration Number: 201735941W