C, Verilog, RTL-to-GDS physical implementation, LLMs, AI-assisted methodologies, LVS, AI coding assistants, systemverilog, GDS tape-out verification, timing closure strategies, timing constraints development, EDA Tools, DRC, scan DFT validation

ASIC (Application Specific Integrated Circuit), Electronic design automation (EDA), team problem solving , Static Timing Analysis, System Verilog, Low-power Design, Design Test Plans, cash checks, Cadence, silicon bringup, Electronic and Electrical Engineering, Block Design, RTL Coding, Logic Synthesis, Preparation of Technical Documents, Interpersonal Skills

Dac, behavior modeling, CMOS analog mixed-signal designs, TX, BG, RX, VerilogAMS, ADC, VerilogA, OSC, Latchup, LDO, Esd, Pll