Tcl, Python, Perl, CI CD integration, assertion-based verification, CAD tool integration, coverage analysis, Uvm, regression automation, formal verification, systemverilog, dynamic verification

Technical Leadership, AHB, Strategic Problem Solving, GLS debugging, systemverilog, Verification Methodology Innovation, Memory Security Boot, Digital SOC design principles, High and Low speed peripherals, Verification Strategy and Architecture, AXI protocols, Advanced Debugging, Processor Interconnect Fabric

rtl development , Spi, Uart, Verilog, System Verilog, I2c, Pcie, front-end design, scripting Python, Design Verification, Cadence Tools, gate-level simulations, UVM-based design verification, DMA engines, micro-architecture development, Synthesis, Timing Closure

Security Solutions, AI-ready Ethernet Fabrics, networking infrastructure, GSP Model, Data Center Switching, Campus Wi-Fi, Cloud Networking Observability, Network Security Automation

Ethernet Services, Embedded PCs, B2B Industrial Sales, Industrial Customers