17:I[832,["6669","static/chunks/app/(Engagement)/similar-jobs/%5Bid%5D/page-8b9fded166c9e5ec.js"],"default"] 1a:I[5878,["6669","static/chunks/app/(Engagement)/similar-jobs/%5Bid%5D/page-8b9fded166c9e5ec.js"],"Image"] 18:T508,{"showUserEngagement":"true","resumeParserSwitch":"false","careerFairLink":"https://www.foundit.sg/events/triumphsg","syndicatedQuickApplyEnabled":"false","bulkApplyMultiSelect":"15","oldLoginCheck":"true","showUploadViaGoogleDrive":"false","heroSectionHeading":"Over 700,000+","gaAccountId":"UA-33929341-1","hideCsCartIcon":"false","triumphEventId":"4","showAppRegistrationPopup":"true","recaptchaV2Switch":"true","srpBrandBooster":"false","dfpSwitch":"true","parseNewResume":"true","parseResumeSwitchDesktop":"false","hideExperienceTypePopup":"true","cleverTapProjectId":"6K9-ZK8-ZZ6Z","copyrightYear":"2020","showDesktopDropboxV2":"false","hideBellNotification":"false","showPassiveJobs":"false","triumphEndDate":"7-3-2024","showTriumphEvent":"true","jobsCount":"200,000+","showPromotionsBox":"true","showCareerFair":"true","parseResumePhoenix":"true","showAppLoginPopup":"false","careerFairName":"Career Fair","resumeParseTime":"30000","showAspireElement":"false","channelName":"Singapore","socialLoginOn":"true","newProfileFlow":"false","socialUrls":"[\"https://www.facebook.com/founditSG/\",\r\n\"https://x.com/foundit_SG\",\r\n\"https://www.linkedin.com/company/foundit-jobs/\",\r\n\"https://www.youtube.com/@foundit_SouthEastAsia\",\r\n\"https://www.instagram.com/foundit_sg/\"]"}19:T54c,

Responsibilities

Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
Verify Logic at ISP level and Digital System level
Optimize Design for less gate count and low power consumption
Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design lead

(Sr.) ISP RTL Design Manager