UVM verification methodology, RTL coding with Verilog, Assembly code programming, RISC-V processor system, System modelling and simulation using emulator and SystemC, SoC architecture and design

Bash, Perl, Verilog, Python, Tcl, Systemc, Embedded C, systemverilog, UVM verification methodology, RISC-V processor system, simulation using emulator, System Modelling, assembly code programming