Gate Level Simulation (GLS), Verilog, Matlab, Python, Adaptive filters, Digital design concepts, Analog and Channel model development, FPGA-based emulation, Sampling, Filters, FPGA emulation, modulation, DSP concepts, system modeling

C, System Verilog, AXI-AMBA protocol variants, Uvm

C, Shell, Verilog, Python, Tcl, Systemc, Test Planning, systemverilog, constrained-random verification, transaction-level modeling, formal verification, power-aware verification, assertions, UVM-based testbench development, NoC bus and interconnect verification

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

DDR, System Verilog, test plan generation, environment development, Design Verification, Uvm, GDDR, memory IP, environment planning, Functional Verification, IP verification, HBM

Perl, Ruby, System Verilog, make, Uvm, Asic verification, Rtl Design, formal verification, TestBench Development