cadence spectre , Python, Analog Mixed Signal Verification, Skill, Xcelium, SystemVerilog-RNM, Uvm, Model vs Schematic Comparison, High-speed Design AMS Verification, Behavioral Modelling, Synopsys VCS FineSim, Verilog-AMS, AMS Designer, Synopsys AMS tools, Cadence Virtuoso, Mixed Signal Modelling, SerDes Verification

Perl, Python, ASICs, Analog behavioral models, System Verilog Programming, Chipsets, Digital Verification

Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor

code coverage , System Verilog, IC verification tools, Cover groups, DIMM, DDR5, DDR4, Uvm, Functional coverage, Assertions, LPDDR5

Svn, C, Shell, Tcl, Verilog, Python, Perl, Git, systemverilog, Cadence Verisium Manager, Uvm, VHDL, Cadence Xcelium

CMOS Circuits, Mentor Calibre, Cadence PVS, LVS, tape-out, productivity-enhancing tools, chip-level floorplanning, ERC, chip-level integration verification, DRC, design scripts, Cadence Virtuoso, BiCMOS circuits, analog block integration, Layout Design