Perl scripting, RTL-to-GDSII implementation, Methodology solutions, CAD automation

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

Perl, Python, Tcl, Sta, Mentor Calibre, primetime, Fusion Compiler, Cadence Innovus, Tempus, EDA Tools, Genus, Synopsys ICC2

Perl, Python, Tcl, UPF-based flows, constraint development, RTL synthesis, Fusion Compiler, Synopsys Design Compiler, Timing Closure, low-power design methodologies, Cadence Genus

PERL, Python, Tcl, Synthesis, Formal Equivalence, DRC, Ir, LVS, EM Signoff

Perl, Python, Tcl, Synopsys Formality, Cadence Conformal, CPF, UPF, Synthesis netlist optimizations, Power domains, Clock gating, Low-power design concepts, Equivalence debugging

routing, Perl, Python, Tcl, IR drop, primetime, Tempus, Cadence Innovus, UPF, physical-aware synthesis, Voltus, 3D heterogeneous integration, RTL-to-GDSII flow, Floor Planning, low-power implementation, Timing Closure, Placement, multi-die assemblies, CPF, Synopsys ICC2