C, Perl, Unix Scripting, Quality Assurance, Python, SPICE Circuit Simulators, Circuit Design, MOSFET Electrical Behavior, Standard Cell Layout Design, Transistor-Level Device Physics, Characterization Modeling, Standard Cell EDA Views, PPA Performance, EDA Tools

Ui Automation, Java, automation testing, Manual Testing, Objective C, Coding, Digital Signal Processing, Scripting, test frameworks, Quality Assurance Engineering, acoustic measurement setups, Test Tools, acoustic fundamentals, audio quality tools

FEA tools, Debugging, Control loop theory, PCB CAD tools, power management, Circuit Design, Data analysis using Excel or JMP, PCB schematic design, Troubleshooting, Lab debugging, Silicon device evaluation, Analog and digital circuit design

OASIS, Python, Shell, Perl, Tcl, PERC, LVS, CDL, Dfm, SVRF-based automation, Verilog netlists, XOR methodologies, layout connectivity, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII

Customization, Spice Simulator, Virtuoso Layout Suite, Mixed Signal Simulation, Virtuoso Analog Design Environment, Standard Cell or Library Characterization, Virtuoso Schematic Editor, PCells, Installation and Licensing Technology file, Design Framework DFII Environment, OpenAccess

Ansys, Silicon Validation, PERL, Debugging, Python, analog simulation, lab equipment, Cadence, Analog Circuit Design, design for test, Mixed Signal Design, EDA Tools, CMOS technology, silicon bring-up, virtuoso, Synopsys, low-power design techniques

Bias and Bandgap Voltage Regulators, jitter and signal equalization techniques, Phase Interpolator, layout and physical verification, CMOS design, High Speed Clock Distribution, Low jitter PLL, CAD tools for circuit simulation, SERDES

Circuit Design, power management, FPGA Development, Embedded Systems, Signal Integrity, Testing Protocols, Hardware Debugging, Pcb Layout