Sta, Layout Design, Spice signoff, GDSII layout design, IR signoff, PPAC optimization, Physical Design, back-end physical implementation

power integrity , Physical Verification, LVS, Block-level physical design, Latchup, ERC, DRC, Digital IC timing layout, Digital IC backend design flow, IC backend design, Backend analysis, Netlist to GDS, Signal Integrity

C, C++, Perl, Fc, Python, Tcl, 3D IC design, FC synthesis, ESD planning, STA signoff, PPA optimization, INVS, SPICE simulation, Pt, PX, STA analysis methods and flows, Power analysis flows, Calibre, RH, Low-power design methodologies

Routing, Perl, Tcl, Clock tree insertion, GDS validation, LVS, Timing Closure, Synthesis, Layout, Placement, DRC, Sign-off, Analog Design, Backend design EDA tools, Noise analysis, Floor Planning, Static Timing Analysis scripts, Deep sub-micron routing, Scan validation, Synopsys ICC2, EDA software, Back-end verification