Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, UPF management, Low-Power Implementation, systemverilog

Java, Kafka, Python, API design, Incident Management, Gcp, Distributed Systems, Kubernetes, Testing, Go, Alerting systems, Flink, Microservices architecture, developer tools, Streaming Data, SDKs, Monitoring

Memory Management, virtualization, System Verilog, Python, Perl, HW-SW debug, Uvm, power management fundamentals, Functional Coverage, DV test bench, Virtual Memory concepts, Scoreboards, Post-Silicon bring-up, coherency protocols, IP Sub System design verification, Assertion, Checkers, Trackers

react.js , Golang, Python, Sql, GenAI, Google BigQuery

Ansys, Silicon Validation, PERL, Debugging, Python, analog simulation, lab equipment, Cadence, Analog Circuit Design, design for test, Mixed Signal Design, EDA Tools, CMOS technology, silicon bring-up, virtuoso, Synopsys, low-power design techniques