data engineering , Advanced Analytics, Agile Methodology, Plm, Usability Testing, Data Governance, Statistical Modelling, Power Bi, Data Warehousing, Machine Learning, Data Visualization, BI and visualization tools, Generative AI Platform Development, Feature Prioritization, User Experience UX Design, User Needs Analysis, User Experience UX, Product Roadmapping, Programming tools, Product Development, Relational Databases, Product Design, Product Lifecycle Management, Customer Feedback Management

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design

Nvme, SAS, Silicon Validation, Pcie, physical implementation, Synthesis, tape-out processes, RTL design using Verilog, Uvm, systemverilog, Dft, Timing Closure, CXL

Silicon Validation, Soc Architecture, Physical Design, manufacturing, digital design verification, Dft

Ecos, Clock Reset UPF, PPA targets, IP integration, constraint and timing convergence, FCR ECR reviews, RTL cleanup, SoC RTL construction, SoC DV test plans

Ecos, Clock Reset UPF, FCR ECR reviews, RTL construction, SoC DV test plans, PPA targets, Fuse Documentation, SOC design, constraint and timing convergence, IP integration

Ecos, SoC DV test plans, RTL construction, FCR ECR reviews, PPA targets, SOC design, Fuse Documentation, Clock Reset UPF, constraint and timing convergence, IP integration