Static Timing Analysis, Python, Tcl, SDC constraint authoring and management, primetime, Fusion Compiler, Physical-Aware Synthesis

Continuous Integration (CI), Java, C, Gerrit, Git, Python, C++, Test Methodologies, Test automation, Shell Programming, Version Control Systems, Ndm, Cadence DB, CDL, LEF, AI-assisted development tools, GDSII, LVS, DRC extraction, LLM-driven techniques, Memory compilers, Tiling, Netlist stitching, Place And Route

redhawk , Tcl Scripting, Python, timing reports, primetime, Fusion Compiler, floorplanning, CTS routing, Tempus, LEC, Cadence Innovus, Physical Verification, setup hold debugging, Voltus, tile block PnR, Calibre, Asic Physical Design, Optimisation, StarRC, Parasitic Extraction, Placement, Synopsys ICC2

conformal lec , Verilog, Python Scripting, Shell, Perl, Clp, Tcl, primetime, Fusion Compiler, Genus, Tempus, Synthesis STA Tools, STA tools

synopsys primetime , Perl, Shell scripting, Python, Tcl, place-and-route, Synthesis, timing exceptions, ECO implementation, MMMC timing analysis, jitter, clock skew

redhawk , Shell, PERL, Verilog, Tcl, place and route methodologies, low power physical design flows and methodologies, Fusion Compiler, physical implementation and analysis tools, timing and signal integrity analysis, Innovus, Calibre, VHDL, power integrity and reliability analysis, power grid planning and implementation, Starrcxt, timing optimization and timing closure, placement and optimization, metal-only ECO implementation, floorplan exploration and optimization, Clock Tree Synthesis