Gate Level Simulation (GLS), Verilog, Matlab, Python, Adaptive filters, Digital design concepts, Analog and Channel model development, FPGA-based emulation, Sampling, Filters, FPGA emulation, modulation, DSP concepts, system modeling

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

System Verilog, SV UVM based test benches, scripting languages such as Perl, HDLs like Verilog, debugging RTL TB issues using Verdi or similar tools

Verilog, cdc, VHDL, RDC, Test plan creation and execution, Formal verification methodologies, Uvm, Constrained random verification techniques, systemverilog

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Shell, Python, Perl, Scripting Languages, DACs, Uvm, SV, Dms, behavioral modeling, Signal Processing, digital RTL, ADC, Synopsys VCS, Analog Mixed Signal, DV, full chip verification, Cadence Virtuoso, verification plan, Oscillators, Pll, Debug

DDR, Pcie, Perl, Vcs, Python, Tcl, Uvm, Axi, Verdi, APB, Questa, systemverilog

Perl, Debugging, Bash, Python, Tcl, SoC Verification, verification environments, standard bus protocols, Uvm, systemverilog