Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

Vcs, Pcie, Fpga, Arinc, Python, Tcl, Xcelium, Questasim, SV-UVM, Rivera-PRO, AXI4, DO-254, Asic verification

code coverage , Verilog, Debugging, FPGA Design, Scripting, Regression Testing, Vcs, systemverilog, Uvm, Testbench Development, Simulation Tools, Functional Verification, Timing Analysis, SoC Verification, Verification Plan, Verdi

Perl, Shell scripting, Python, vManager, Xcelium, Cadence environments, JasperGold, UVM methodologies

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

Perl, Python, Synopsys VCS, Cadence Xcelium, Uvm, systemverilog