Routing, power analysis, Physical Verification, Physical Design, floorplanning, Timing Closure, Placement, DRC, LVS, Signal Integrity, Rtl Design

Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Tcl, Python, Perl, Physical Design flow, UPF, Fusion Compiler, Physical Verification, Innovus, Sta, ICC2, primetime, Tempus, low power design, CPF, MMMC concepts

Physical Design, DFT Implementation, Layout Extraction, Rtl Design

power integrity , Routing, CTS, primetime, Fusion Compiler, floorplanning, ICC2, PDN Placement, Physical Verification, Calibre, Innovus, SoC ASIC Physical Design, Timing Closure, signoff methodologies

Multi-mode multi-corner (MMMC) timing closure, Network-on-Chips (NoC), System IP components, Physical design implementation, floorplanning, Uncore subsystems, Timing budgeting, Place-and-route, Coherent CPU clusters, Timing Closure, Synthesis, RTL-to-GDSII implementation, Partitioning, Hierarchical design techniques, Sign-off