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As a Design Verification Manager, you are expected to carry out the following responsibilities.

Be in-charge of a passionate verification team that is constantly pushing the limits
Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
Conduct thorough test plan reviews systematically and execute the plan on-time with high quality.
A