power optimization , Routing, Physical Verification, Timing Analysis, IR drop, Power Planning, Physical design implementation, floorplanning, LVS, EM analysis, Physical verification concepts, ECO implementation, Timing Closure, Setup hold fixing, Placement, DRC, Clock optimization

ERC, DRC, block level floor-planning, top-level layouts, LVS, physical reliability verifications

routing, Perl, Static Timing Analysis, Tcl, Synthesis, GDS validation, synthesis DFT, LVS, power and noise analysis, scan validation, back-end verification, Layout, RTL to GDS, Floor Planning, DRC, Timing Closure, Placement, backend design EDA tools, clock tree insertion, sign-off, Synopsys ICC2, Netlist to GDS, EDA software