VLSI FIFO arbitration techniques, static QCs viz LINT CDC RDC CLP VCLP, design and integration for various in-house vendor IPs subsystems and SoC, RTL Coding, QC tools flows and IPXACT, constraints like SDC UPF

Clp, Pcie, Qc Tools, IPXACT, cdc, Vlsi, LINT, FIFO, UPF, AMBA, arbitration techniques, SDC, RDC, RTL Coding, VCLP

C, Pcie, Verilog, Sata, Matlab, System Verilog, Python, protocol analyzers, high-speed transceivers, HDL Simulation Tools, spectrum analyzers, FPGA tools, Axi, VHDL, Wishbone, Xilinx Vivado Design Suite, Avalon, high-speed oscilloscopes