power optimization , Routing, Logic Design, Perl, Python, Tcl, Circuit Design, floorplanning, Mentor, Cadence, Signal Integrity, LVS, Digital Design Fundamentals, Physical Verification, Physical Design, ERC, Placement, Timing Closure, DRC, Timing, EDA Tools, Synopsys, Rtl Design

C, Tcl, Routing, Perl, Physical Verification, LEC, Calibre, Innovus, floorplanning, EDA Tools, Clock Planning, ICC2, primetime, Placement, Timing Closure, Physical Design Implementation

Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

Tcl, Python, Perl, Physical Design flow, UPF, Fusion Compiler, Physical Verification, Innovus, Sta, ICC2, primetime, Tempus, low power design, CPF, MMMC concepts

power optimization , Perl Scripting, CTS, Block level PnR convergence, Cadence Innovus, LVS, Physical Implementation, Timing convergence, Physical Verification, Timing Closure, DRC, PDN, STA concepts, Floor-planning, PD implementation of PPA critical Cores, Place And Route, Synopsys ICC2, formal verification, Clocking architecture

redhawk , Python Scripting, Pvs, Perl, Tcl, QRC, primetime, ICC2, Tempus, Voltus, Innovus, Calibre, Physical Design, Starrcxt

layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs