C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog, SVA

Shell, Perl, Scripting, Tcl, debug methodologies, automation using Python, Uvm, assertion-based verification, systemverilog, regression frameworks, coverage closure, formal verification, Functional Verification

Sqlalchemy, Grafana, React, Typescript, Terraform, Postgres, Python, Sentry, Redis, FastAPI, Kubernetes, GitOps, PostHog, Tailwind, TurboPuffer, GitHub Actions, Temporal, Next.js, OpenTelemetry, Pydantic, GKE, LLMs, Anthropic, AKS, Expo, Argo CD, OpenAI, Gemini

Numpy, Git, Pytorch, Pandas, Python, OpenAI’s GPT models, Hugging Face, prompt engineering

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

Linux, Storage Systems, Nvme, Python, Pcie, Windows, Automation Frameworks, SSD architecture, AI-powered productivity tools, validation tools

Perl, Bash, Python, Tcl, C, shell scripting, simulation and emulation environments, verification methodologies, Linux Unix environment, SystemVerilog UVM, test plan creation and execution

manufacturing processes , Silicon Characterization, Data Automation, Yield Analysis, Product Reliability Assessment, Reporting, Failure Analysis, Statistical Techniques, process monitoring, Reliability Analysis, Scripting or Analytics Tools, Data Analysis, Semiconductor Product Yield Engineering, Product Lifecycle Management, Root Cause Investigation