Liberty .lib, Python, Tcl, pulse-width verification, OCV, setup hold analysis, ETM timing model generation, ONFI PHY, Cadence Tempus, DDR PHY, Innovus, MMMC timing analysis, Cadence digital implementation and signoff flow, IO Expander, POCV methodologies, Genus, AI ML-enabled EDA methodologies, recovery removal checks, SDF generation, AOCV

synopsys primetime , static timing analysis, Soc, Perl, Python, Tcl, low-power techniques, Electronic Design Automation EDA tools, digital design fundamentals, Multi mode timing constraint development, STA tools, Cadence Tempus, ASIC, clocking architectures, timing constraints SDC, timing signoff

Signal Integrity, SDC constraints, MCMM, MMMC, setup hold analysis, timing optimization, timing ECOs, Timing Analysis, Cadence Tempus

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, UPF management, Low-Power Implementation, systemverilog

memory controllers , Python, Computer Engineering, vector processors, low-precision or mixed-precision numerics, architecture and micro-architecture design, memory hierarchy, Computer Science, DSP processors, DRAM technologies, HBM, Electrical Engineering, networking ASICs

synopsys primetime , Perl scripting, Static Timing Analysis, SDC constraints, RTL Synthesis, STA timing constraints, mmc, Timing optimization, Critical path analysis, ASIC SoC implementation and signoff methodologies, Setup hold analysis, Timing Closure, MCMM, Synopsys Design Compiler, ECOs and timing fixes

Tcl Scripting, EDA timing tool competence, primetime, spyglass, Tweaker, Fishtail, SDC knowledge, GCA, Synopsys Design Compiler, DMSA

synopsys primetime , Perl, Python, Tcl, Setup Hold closure methodologies, MMMC timing signoff, ECO and timing convergence techniques, SOCV AOCV derates, Cadence Tempus

synopsys primetime , Perl, Shell scripting, Python, Tcl, place-and-route, Synthesis, timing exceptions, ECO implementation, MMMC timing analysis, jitter, clock skew