Perl, Python, ASICs, Analog behavioral models, System Verilog Programming, Chipsets, Digital Verification

cadence spectre , Python, Analog Mixed Signal Verification, Skill, Xcelium, SystemVerilog-RNM, Uvm, Model vs Schematic Comparison, High-speed Design AMS Verification, Behavioral Modelling, Synopsys VCS FineSim, Verilog-AMS, AMS Designer, Synopsys AMS tools, Cadence Virtuoso, Mixed Signal Modelling, SerDes Verification

Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage

DDR, Pcie, Ethernet, GIC, CMN, Low-Speed Peripherals, SMMU, RISC-V Cores, eMMC, CoreSight, SoC-level Design Verification, SV, Low-Power Verification, ARM v8 v7 Cores, Uvm, UPF