C, C++, Bash, Perl, Verilog, Python, Tcl, IP architecture, Debug, stimulus development, verification planning, Digital Design, Uvm, systemverilog, scoreboards, assertions, functional coverage

Perl, Verilog, Gdb, Python, SV-UVM, e-specman

Uart, Nvme, Verilog, I2c, Pcie, Flash, system debug infrastructure, Uvm, system memory hierarchy, AMBA bus protocols, systemverilog, digital ASIC design and verification, formal verification, ARM cores and related infrastructure, CXL, DRAM, CPUSS C-based verification, multi-core SOC, SSP