System Verilog, Building test benches from scratch, Data path verification performance tests, Gate level simulation, ASIC verification using UVM, formal verification

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Tcl Scripting, Doors, DO-254 development process, Electronics Electrical Engineering, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, RTL development using VHDL, Hardware system design knowledge of digital logic, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero

Fpga, Perl, Python, object-oriented design, RTL, test plan development, emulation platforms, Uvm, systemverilog, automation scripts

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

System Verilog, Building test benches from scratch, ASIC verification using UVM

Vcs, Pcie, Python, Perl, Ethernet, Tcl, Xcelium, Uvm, Testbench Architecture, LPDDR4, Functional Coverage, Verdi, UCIe, systemverilog, Axi, MIPI, Constrained Random Verification, APB, DVE, USB4, USB3, Questa, CXL, DDR5, DDR4, AHB, SVA

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

code coverage , Vcs, Nlp, Test Plan Creation, verification closure, UVM methodology, non-NLP simulations, VS Code, systemverilog, GLS, GitHub CoPilot, debugging of complex mixed signal designs, testbench architecture, verification of mixed signal IP Design, Git version control, constraint-random test generation, failure root cause analysis, waveform debugs, functional coverage