bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

Perl, Python, Tcl, Timing Closure STA, RTL-to-GDSII Execution, Red Hawk, Programming Scripting, Fusion Compiler, LEC, Tempus, Cross-Functional Collaboration, Physical Formal Verification, Calibre, Innovus, primetime, PPA Optimization, EDA Tools, VCLP

automation, Python, Tcl, place-and-route, Cadence Innovus, Timing Analysis, Physical Verification

Pytest, Pytorch, Deep Learning, Tensorflow, Python, Linux, Machine Learning, Transformers

Schematic design, MATLAB, Python, Synopsys Custom Compiler, BERTs, Spectre, Hspice, Cadence Virtuoso, Layout interaction, behavioral modeling, Lab measurements, BER estimation, High-speed oscilloscopes, Post-layout verification, Design sign-off, Jitter budgeting, Parasitic Extraction, Silicon bring-up

Perl, Python, Tcl, FineSim, Matlab Simulink, Cadence Xcelium, CustomSim, mixed-signal verification, Uvm, systemverilog, Spectre, Synopsys VCS, AMS Designer, Cadence Virtuoso, Verilog-A

Github, virtualization, OpenStack, Dns, Firewalls, routing, DHCP, Gcp, Terraform, shell scripting, Ansible, Pure Storage, Azure, Python, Kubernetes, AWS, networking fundamentals, Linux systems administration, Dell PowerStore, Infrastructure-as-Code