Tensorflow, Machine Learning, Pytorch, Linux, Python, Pytest, Deep Learning, Transformers

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, DFT micro-architecture, Synopsys Tetramax, EDA Tools, Scan, Mentor Tessent

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, digital design principles, verification methodologies, RTL design using Verilog, clocking resets, Simulation, Timing Analysis, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques

network infrastructure, C, Computer Networking, Pcie, Routing Protocols, I2c, Linux Kernel, L2 Switching, hash memories, SERDES, sonic, Networking OS, Enterprise Data Center, carrier network switching, NOS, DMA controllers, Marvell Switching Networking products, debugging skills, MDIO, TCAM, SAI