Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification

Spi, I2c, Uart, Pcie, Usb, Noc, cdc, SoC IP Design, AMBA protocols, Network on Chip

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

System Verilog, C, Bug Tracking Tool, Git, Models for performance verification, Synopsys, Monitors, Transactors, Performance test plan development, Cadence, RTL simulations

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi