Matlab, Post layout parasitic extraction, Schematic generation and simulation, Worst case identification, Process technologies tradeoffs, Monte Carlo analysis, Simulation verification, Block level topology selection, IC system partitioning, Physical layout management, AMs, Analog Circuit Design, Signal grounding and routing tradeoffs, Architectural tradeoff analysis, Spectre, Cadence tool set, Simplis

System-Level Trade-off Analysis, IP Integration and Sub-system Ownership, Analog IP Architecture Technical Direction, Silicon Readiness Debug Learning Loop, Analog-Digital Interface Mixed Signal Integration, Analog IP Quality Sign-off Framework, Sub-system Modelling, Simulation Verification, Analog Mixed-Signal Power IC design, Cross-Functional Leadership, Behavioural Modelling, Analog IP Spec Derivation Optimization, EDA Tools, Continuous Technical Review Mentoring, Innovation Circuit Excellence, device physics, Reusable IP Design Methodology

high-speed TX, analog mixed signal design, EDA Tools, transistor capacitor matching, transistor level circuit design, SERDES, Cadence, compensation techniques, Siemens, noise analysis, Synopsys, Pll