System Verilog, Building test benches from scratch, Data path verification performance tests, Gate level simulation, ASIC verification using UVM, formal verification

static timing analysis, System Verilog, hardware modeling, lint checks, Verilog V2K, logic debug environments, high-frequency optimization, power aware design, UPF, Rtl Design, low-power logic design, Cross-clock domain crossings

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

Perl, Python, Tcl, CMOS Analog Circuit Design, StarRC, Calibre xRC, Assembler, ADE XL, Cadence Virtuoso, Spectre

Uart, Spi, Shell, Verilog, I2c, Python, Tcl, LINT, Design Compiler, cdc, LEC, UPF, systemverilog, AMBA, Axi, RDC, APB, Genus, CPF, AHB

MATLAB, Autocad, Pcb Design, Power Systems, Signal Processing, Embedded Systems, Circuit Analysis, Microcontrollers, Project Management, Regulatory Compliance, Solid Work

Shell, C, Perl, Verilog, Python, Tcl, EDA Tools, UVM methodology, systemverilog

Soc, Rtos, Python, Embedded Linux, inter-processor communication, secure boot development, BootROM, bare-metal environments, embedded firmware systems, bootloaders, power-management, platform firmware development, FPGA debug

constraint analysis , Perl, Verilog, System Verilog, Tcl, Sta, Synthesis, Simulation, synthesis logic equivalence, timing constraints generation, STA tools and flow, design for test, IP ASIC timing constraints generation, Dft, formal verification, backend related methodology and tools, LINT, Timing Closure, Design Methodologies, functional coverage, timing closure of various test modes

Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools