bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging

Pcie, Version Control, Ethernet, RTL synthesis, Documentation, Timing Closure, verification processes, silicon bring-up, bare metal firmware development, SERDES, AI tools like Cursor

Java, C, Python, SIMD vectorization, Cache-aware execution, Performance profiling, Parallel execution strategies, qemu, Benchmarking, Optimization

VLSI FIFO arbitration techniques, static QCs viz LINT CDC RDC CLP VCLP, design and integration for various in-house vendor IPs subsystems and SoC, RTL Coding, QC tools flows and IPXACT, constraints like SDC UPF

Tcl Scripting, Perl, 22nm FINFET nodes, LVS, Density, Parasitic noise, Calibre, Supply consideration, Esd, Antenna, Double patterning, Device matching, Layout dependent effects, Signal shielding, Semiconductor device physics, Latchup, Cadence Virtuoso XL VXL, Skill, EMIR, 16nm, Noise isolation, Latch up shielding, 12nm, DRC, 7nm, Isolation, Well’s substrates, Layout matching

redhawk , Innovus, primetime, Synthesis, Physical Design, tapeout