Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Fpga, Perl, Python, object-oriented design, RTL, test plan development, emulation platforms, Uvm, systemverilog, automation scripts

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

System Verilog, C, Bug Tracking Tool, Git, Models for performance verification, Synopsys, Monitors, Transactors, Performance test plan development, Cadence, RTL simulations