Perl, Linux, Verilog, SDF, Firmware, Tcl, Path-Delay fault models, FPGA synthesis, MBIST, RTL, Gate, iJTAG, Dft, ATPG, Scan, Stuck-At, Transition

PYTHON, PERL, Verilog, Tcl, ATPG vector generation, DFT concepts, Digital circuit design, Logic BIST design and debug, Memory BIST insertion and verification, Scan compression, Static timing principles, IEEE 1149, Scan Insertion, VHDL, Testbench generation, device physics, Simulation and debug

Perl, Python, Tcl, Sta, Synthesis, DFT EDA tools, Dft

boundary scan , Perl, Python, Tcl, IC logic design flows, STA timing analysis, IC verification flows, DFT design, ATE test patterns, pattern debugging, test issue analysis, MBIST, verification of automotive-grade SoCs, EDA tools from Synopsys, coverage optimization, ATPG, Scan, IC DFT

SDF, Fpga, Perl, Tcl, Python, Dft, ATPG, Sta, RTL, Gate, MBIST

Perl, Python, Tcl, Sta, Synthesis, Dft, DFT EDA tools