regulators , temperature sensors , Dll, Reference Circuits, PMU circuits, RC Oscillators, Validation, Mixed-Signal Design, Crystal Oscillators, Analog design and simulation tools, Switching Regulators, Pll, Signal Chains, Oscillator, Precision Comparators, Analog IC Design, characterization, Debug, Silicon bring-up

synchronicity , Unix, Perforce, Python, Shell Scripting, Git, Perl, Tcl, substrate noise analysis, Skill, Cadence custom IC Virtuoso platform, Cadence SKILL, starRC, Layout Automation, Calibre Physical Verification, ICV LVS, Analog Design environment, EMIR drop, agentic AI flows, finesim, Parasitic Extraction, PrimeSim, Virtuoso suite, SVRF

layout interaction, silicon bring-up, design sign-off, behavioral modeling, Analog Circuit Design, mixed-signal IC design, post-layout verification, high-speed oscilloscopes, Synopsys Custom Compiler, Spectre, high-speed interfaces, BERTs, Compliance Testing, Parasitic Extraction, Cadence Virtuoso, Hspice

Verification, high-speed TX, switched-cap circuits, ADC architectures, feedback and compensation techniques, Timing Analysis, transistor level circuit design, SERDES, Cadence, bias op-amps, capacitor matching, tapeout, top chip integration, AI tools, Silicon Bring up, bandgaps, noise analysis, TCAD, analog mixed signal design, CMOS pixel design techniques, CMOS image sensors, LDOs, Dft, Pll, Simulation

UNIX, Layout tradeoffs, End to end design flow, CMOS BiCMOS fabrication processes, Modeling Tools, MOS transistors, Analog Circuit Design, Poles zeros compensation, Signals systems and transforms, Mixed Signal Design, Production test applications, Feedback systems, device physics, Circuit simulation tools, AC DC analysis, Loop dynamics, Analog Power IC design, Layout verification tools

Pvs, R3D, analog layout matching techniques, Floor Planning, PowerFET, LVS, Analog layout design, package substrate interactions, EM, Ir, Calibre, PEX, Packaging, virtuoso, IC Layout design, Xl, Esd, DRC, die-to-bump connectivity, CAD Tools