Synopsys IC Validator, Custom Compiler, 7nm FinFET technology, Cadence Virtuoso Layout Suite, ERC checks, Cadence Pegasus, high-speed analog and mixed-signal layout design, DRC, Calibre DRC LVS PEX, LVS

High-speed SERDES IO PHY Layout design, Signal integrity issues, Analog IO design principles, Automated PnR, Block PnR, CMOS and FinFET technologies

Dac, Custom IP Development, LVS, ADC, Mentoring engineers, PHY Power Management, LDO, ERC, DRC, Analog Mixed-Signal Layout Design, Conducting reviews, Antenna and EMIR verification signoff methodologies, Leading layout activities, High-Speed Analog layouts, Pll

Vdc, ADC, Charge pump, density, Antenna, noise fixes, Vlsi Design, custom analog layout design, Virtuoso XL, EDA Tools, RV high voltage flows, LDO, scripting skills, layout validation, Circuit Design, DRCs