Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage

DDR, Pcie, Ethernet, GIC, CMN, Low-Speed Peripherals, SMMU, RISC-V Cores, eMMC, CoreSight, SoC-level Design Verification, SV, Low-Power Verification, ARM v8 v7 Cores, Uvm, UPF

Verilog, System Verilog, Coverage Closure, Assertion Checker Development, Functional Coverage Development, Testcase Planning Development, UVM Testbench Coding, Design Verification Failure Debugging

code coverage , Design Verification Engineer, Low Power Verification Engineer, Power-Aware Verification Engineer, ASIC Design Verification Engineer, systemverilog, Uvm, Constrained Random Verification, Gate-Level Simulation, Timing Simulation, PAGLS, Testbench Development, VIP Integration, Coverage Closure

Perl, Shell scripting, Python, vManager, Xcelium, Cadence environments, JasperGold, UVM methodologies

C, Perl, Computer Architecture, Ruby, Python, Assembly start up code, Makefiles, Stimulus generation, Uvm, Testbenches, Pre-silicon verification, Formal verification methods, Linker scripts, Post-silicon FPGA validation

Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog

Perl, Python, Synopsys VCS, Cadence Xcelium, Uvm, systemverilog