Routing, Physical Verification, Physical Design, EDA Tools, floorplanning, Placement, Timing Closure, DRC, LVS

Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs

Block level and Top-level physical implementation, Place and Route processes, Synthesis for high-speed designs, Physical Verification, Physical Design for complex Chiplets, Unix/Linux environment

static timing analysis, routing, Innovus, LVS, Parasitic Extraction, Fusion Compiler, DRC, Placement, floorplanning, Clock Tree Synthesis, ICC2

Block level and Top-level physical implementation, Place and Route processes, Synthesis for high-speed designs, Physical Verification, Physical Design for complex Chiplets, Unix/Linux environment

Physical Design, DFT Implementation, Layout Extraction, Rtl Design

power optimization , Eda, Tcl Scripting, Python, power analysis, Sta, Agentic AI methodologies, DVFS, LEC, AI-driven optimization, Place And Route, UPF, Physical Verification, Timing Power closure, Asic Physical Design, Physical Verification, full chip and block level floor-planning, Eco, multi-Vt power domains, RTL to GDS Flow, CPF, LLM-assisted debugging, autonomous agents

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC