analog filters , layout verification , Test Automation, Circuit Design, SPICE Simulation, IC layout, Signal Integrity, power management, RF Design, Mixed-Signal

Perl, Python, Charge pump, VCO, PLL Loop Dynamics, Loop filter, Analog Circuit Design, PI Deserializer, Pfd, DCO, High speed dividers, adexl, TDC, Sampler, Bias Reference, virtuoso, LDO, High speed TX and RX Equalizer, SPICE simulators

C, Spi, Verilog, I2c, Python, C++, Uart, Perl, Real Number Modeling, LNA, Analog IC design, LVS, Bias bandgap, VHDL, Cadence IC design tools, Filters, LDO, Layout experience using Cadence flow, VerilogAMS, Charge pump, Opamp, systemverilog, MIPI, DRC, VerilogA

Matlab, Worst case identification, Monte Carlo analysis, Block level topology selection, AMs, Analog Circuit Design, Spectre, Cadence tool set, Top level simulation, Simplis, IC system partitioning and architectural tradeoff analysis, Hand analysis and IC transistor level implementation, Post layout parasitic extraction, Schematic generation and simulation on modern CAD tools

Dac, analog mixed-signal IC design, Cadence, Spectre, Calibre, low-noise amplifiers, virtuoso, ADC, AFE circuits, mixed-signal systems, signal conditioning components, Filters

Modeling, automation techniques, reusable intellectual property, circuit design verification, silicon correlation, analog and mixed-signal IC design, semiconductor device physics, CMOS technologies, AI-driven engineering tools, product qualification, DRAM, advanced process nodes

Cadence Virtuoso, High-Speed ADC Design, EDA Tools, Post-silicon validation, Analog IC Design, Mixed-Signal IC Design

CMOS BCD Analog Circuits, power management, Design Reviews, Mass production test plan, Quality assurance test plan