Scripting, Perl, Tcl, Calibre, Innovus, Assura, Cv, ICC2, Cadence, EDA Tools, Verification Tools

static timing analysis, Synthesis, verification methodologies, design optimization techniques, low-power design methodologies, Power Planning, Place And Route, FC Innovus, Clock Tree Synthesis

C, Tcl, Routing, Perl, Physical Verification, LEC, Calibre, Innovus, floorplanning, EDA Tools, Clock Planning, ICC2, primetime, Placement, Timing Closure, Physical Design Implementation

redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques

Tcl, Routing, Perl, Timing Closure, Timing Constraints, Power Integrity Analysis, primetime, Physical Verification, Floor Planning, Methodologies, Calibre, Cadence Tools, CTS, Innovus, Sta, ICC2, Placement, Tk, PT-PX, sub-micron technology, Netlist2GDSII Implementation

Tcl, Python, Perl, Physical Design flow, UPF, Fusion Compiler, Physical Verification, Innovus, Sta, ICC2, primetime, Tempus, low power design, CPF, MMMC concepts

layout verification , automation, Python, Computer Engineering, System Verilog, Scripting, Tcl, Computer Science, EMIR convergence, Electrical Engineering, design rules, low power designs